1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a multi-level memory cell.
2. Description of the Related Art
Electrically erasable programmable read-only memory (EEPROM) is a type data storage device that allows multiple data writing, reading and erasing operations. In addition, the stored data will be retained even after power to the device is removed. With these advantages, it has been broadly applied in personal computers and electronic equipment.
A typical EEPROM has a floating gate and a control gate fabricated using doped polysilicon. When electrons are injected into the floating gate during a programming operation, the electrons distribute evenly within the polysilicon floating gate layer. However, if the tunneling oxide layer underneath the polysilicon floating gate layer contains some defects, a leakage current may flow from the device and compromise the reliability of the device.
To prevent the flow of a leakage current, an EEPROM with a stacked gate structure having an oxide/nitride/oxide (ONO) composite layer known as a SONOS read-only memory is currently used. Here, the silicon nitride layer replaces the polysilicon floating gate as the charge-trapping layer. Because electrons are injected into the silicon nitride layer mainly through a localized region, the leakage current is less sensitive to any defects in the tunneling oxide layer.
FIG. 1 is a schematic cross-sectional view of a conventional SONOS read-only memory (ROM) cell. As shown in FIG. 1, the SONOS ROM cell includes a substrate 100, a composite layer 114 that includes a silicon oxide layer 102, a silicon nitride layer 104 and a silicon oxide layer 106 (ONO), a gate 108, a pair of spacers 110, a channel 118 and a pair of source/drain regions 112. The silicon oxide layer 102, the silicon nitride layer 104 and the silicon oxide layer 106 constituting the composite layer 114 are sequentially formed over the substrate 100. The gate 108 is formed over the composite layer 114. The gate 108 and the composite layer 114 together form a gate structure 116. The spacers 110 are positioned on the sidewalls of the gate structure 116. The source/drain regions 112 are formed in the substrate 100 on each side of the gate structure 116. The channel 118 is formed in an area underneath the silicon oxide layer 102 between the source/drain region 112.
To program data into the aforementioned SONOS ROM cells, the so-called Fowler-Nordheim tunneling effect is utilized. First, a voltage is applied to the gate 108 so that a large electric field is setup between the gate 108 and the substrate 100. The electric field induces the electrons in the substrate 100 to inject from the channel 118 through the tunneling dielectric layer 102 into the charge-trapping layer 104, thereby increasing the threshold voltage of the transistor. In this way, a single bit of data is programmed into a memory cell.
In a conventional SONOS ROM, a single bit of data is stored within each memory cell. However, with the expansion of computer software applications, the need for high storage capacity memory increases exponentially. To produce a deep sub-micron memory with a large memory capacity, the structure and some of the steps for forming the SONOS ROM must somehow be modified.